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====SSE registers==== SSE discarded all legacy connections to the FPU stack. This also meant that this instruction set discarded all legacy connections to previous generations of [[SIMD]] instruction sets like MMX. But it freed the designers up, allowing them to use larger registers, not limited by the size of the FPU registers. The designers created eight 128-bit registers, named XMM0 through XMM7. (''Note'': in AMD64, the number of SSE XMM registers has been increased from 8 to 16.) But the downside is that operating systems had to have an awareness of this new set of instructions in order to be able to save their register states. So Intel created a slightly modified version of Protected Mode, called [[Enhanced Mode]] which enables the usage of SSE instructions, whereas they stay disabled in regular Protected Mode. An operating system that is aware of SSE will activate Enhanced Mode, whereas an unaware operating system will enter only into Protected Mode. SSE is a SIMD instruction set that works only on floating point values, like 3DNow!. However, unlike 3DNow!, it severs all legacy connection to the FPU stack. Because it has larger registers than 3DNow!, SSE can pack twice the number of single precision floats into its registers. The original SSE was limited to only [[single precision]] numbers, like 3DNow!. The SSE2 introduced the capability to pack [[double precision]] numbers too, which [[3DNow!]] had no possibility of doing since a double precision] number is 64-bit in size which would be the full size of a single 3DNow! MMn register. At 128-bit, the SSE XMMn registers could pack two double precision floats into one register. Thus SSE2 is much more suitable for scientific calculations than either SSE or 3DNow!, which were limited to only single precision.
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