Codex Gamicus
Basic Information

SSE2, or Streaming SIMD Extensions 2, is an IA-32 SIMD instruction set designed by Intel Corporation, and based upon its predecessor, SSE. SSE2 extends the functionality of SSE while also rendering SSE's predecessor, MMX, completely obsolete. SSE2 was first introduced by Intel in their Pentium 4 line of processors.

SSE2 adds support for 64-bit double-precision floating point operations and for 64-bit, 32-bit, 16-bit and 8-Bit integer operations on the eight 128-bit XMM registers first introduced with SSE. SSE2 adds no additional program states to that provided by SSE.

The addition of 128-bit integer SIMD operations allows the programmer to completely avoid the eight 64-bit MMX registers "aliased" on the original IA-32 floating point registers. This permits the mixing of integer SIMD and scalar floating point operations without the time-consuming mode switching required in MMX and SSE.

Other SSE2 extensions include a set of cache-control instructions intended primarily to minimize cache pollution when processing indefinite streams of information.

Rival chip-maker AMD would later add support for SSE2 with the introduction of their Opteron and Athlon 64 lines of 64-bit processors in 2003. However, AMD also chose to extend SSE2 out beyond Intel's original implementation by doubling the number of XMM registers, from eight to sixteen. The additional registers are only visible when the processor is running in 64-bit mode, known as AMD64. Intel also eventually adopted the additional XMM registers that AMD introduced when Intel announced that it would adopt the AMD64 architecture, branding their implementation as EM64T. This arrived in late 2004, with the Pentium 4 600 series, which also added NX Bit Support.